Energy-aware Scheduling and Fault Tolerance Techniques for the Exascale Era - STIC-AmSud Project Grant 99999.007556/2015-02
The main goal of the EnergySFE research project is to propose fast and scalable energy-aware scheduling and fault tolerance techniques and algorithms for large-scale highly parallel architectures. To achieve this goal, it will be crucial to answer the following research questions:
Another important goal of the project is to establish a perennial collaboration between international partners from Brazil (UFSC and UFRGS), France (CNRS) and Ecuador (ESPE), as well as to promote knowledge transfer between them.
P.H. Penna, M. Castro, P.D.M. Plentz, H.C. Freitas, F.B., J-F. Méhaut. “BinLPT: A Novel Workload-Aware Loop Scheduler for Irregular Parallel Loops”. In: Simpósio em Sistemas Computacionais de Alto Desempenho (WSCAD), 2017.
A.D. Pereira, R.C.O. Rocha, M. Castro, L.F.W. Góes, M.A.R. Dantas. “Extending OpenACC for Efficient Stencil Code Generation and Execution by Skeleton Frameworks”. In: International Conference on High Performance Computing & Simulation (HPCS), 2017.
D. Oliveira, L.L. Pilla, M. Hanzich, V. Fratin, F. Fernandes, C. Lunardi, J.M. Cela, P.O.A. Navaux, L. Carro, P. Rech. “Radiation-Induced Error Criticality in Modern HPC Parallel Accelerators”. In: IEEE Symposium on High-Performance Computer Architecture (HPCA), 2017.
D. Oliveira, L.L. Pilla, N. DeBardeleben, S. Blanchard, H. Quinn, I. Koren, P.O.A. Navaux, P. Rech. “Experimental and Analytical Study of Xeon Phi Reliability”. In: International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 2017.
P.H. Penna, E.C. Inacio, M. Castro, P.D.M. Plentz, H.C. Freitas, F. Broquedis, J.-F. Méhaut. “Assessing the Performance of the SRR Loop Scheduler with Irregular Workloads”. In: International Conference on Computational Science (ICCS), 2017.
P. Ramos, V. Vargas, M. Baylac, F. Villa, S. Rey, N.E. Zergainoh, R. Velazco. “Error-rate prediction for applications implemented in Multi-core and Many-core processors”. In: Error-rate prediction for applications implemented in Multi-core and Many-core processors (RADECS), 2017.
V. Vargas, P. Ramos, V. Ray, C. Jalier, R. Stevens, B.D. de Dinenchin, M. Baylac, F. Villa, S. Rey, N.E. Zergainoh, J.F. Méhaut, R. Velazco. “Radiation Experiments on a 28nm Single-Chip Many-core Processor and SEU error-rate prediction”. In: IEEE Transactions on Nuclear Science, 2017.
E.H.M. Cruz, M. Diener, L.L. Pilla, P.O.A. Navaux. “A Sharing-Aware Memory Management Unit for Online Mapping in Multi-core Architectures”. In: International European Conference on Parallel and Distributed Computing (Euro-Par), 2016.
M. Castro, E. Francesquini, F. Dupros, H. Aochi, P.O.A. Navaux, J.-F. Méhaut. “Seismic Wave Propagation Simulations on Low-power and Performance-centric Manycores”. In: Parallel Computing, 2016.
M.A. Souza, P.H. Penna, M.M. Queiroz, L.F.W. Góes, H.C. Freitas, M. Castro, P.O.A. Navaux, J.-F. Méhaut. “CAP Bench: A Benchmark Suite for Performance and Energy Evaluation of Low-Power Many-Core Processors”. In: Concurrency and Computation: Practice and Experience, 2016.
P.H. Penna, M. Castro, H.C. Freitas, F. Broquedis, J.-F. Méhaut. “Design Methodology for Workload-Aware Loop Scheduling Strategies Based on Genetic Algorithm and Simulation”. In: Concurrency and Computation: Practice and Experience, 2016.
P. Ramos, V. Vargas, M. Baylac, F. Villa, S. Rey, J. Clemente, N-E. Zergainoh, J-F. Méhaut, R. Velazco. “Evaluating the SEE sensitivity of a 45nm SOI Multi-core Processor due to the 14 MeV Neutrons”. In: IEEE Transactions on Nuclear Science, 2016.